A number of conventional approaches to implementing FIFO memories are available. One conventional approach uses flip-flops to implement a FIFO. Such an approach is relatively easy to implement, but is expensive in terms of area and power.
Another conventional approach uses a Random Access Memory (RAM) with a byte enable input. 2 ports are implemented for writing and 2 ports are implemented for reading. Implementing a RAM as part of a FIFO is also expensive.
Another conventional approach uses two RAM modules with one port for reading and one port for writing. One RAM module is used for odd lines and the second RAM module is used for even lines. With such an approach, every access can be for two consecutive FIFO lines in one cycle since every module is accessed for maximum 1 line. Each of the RAM modules has a byte enable input, so such an implementation is more expensive to implement than an approach without a RAM memory with a byte enable input.
Referring to FIG. 1, one conventional approach is shown. Each of the memory cells is implemented as a flip-flop. When accessing the FIFO for a read, the read flip-flops will be accessed and the data will be read and sent out as 16 bytes read data. When accessing the FIFO for write, the write flip-flop will be accessed and the write data will be written. While such an approach is flexible, and can separately access every bit, such an approach uses a large amount of area and consumes a large amount of power.
It would be desirable to implement a FIFO that may handle a variable size of data and may (i) perform push and pop operations in one clock cycle, (ii) use a RAM with only one port for a read operation and one port for write operation, and/or (iii) be implemented without the need for a byte enable input.